With constant down-scaling and increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits, semiconductor devices, such as transistors, diodes, capacitors and the like, need to continuously reduce space between active (Rx) regions on a semiconductor substrate. More specifically, as integrated circuits are scaled down, the shallow trench isolation (STI) regions used to electrically isolate Rx regions must also be scaled down.
Conventionally, multiple Rx regions in a semiconductor integrated circuit typically include arrays of parallel extending fins having distal ends abutting the edges of each Rx region. By way of example, this is particularly the case for FinFET technology at the 14 nm node and beyond. The fin arrays are terminated by dummy gates, which extend laterally across the distal ends of the fins at the edges of the Rx regions. The dummy gates are used to induce symmetrical epitaxial growth of source/drain regions (S/D regions) on the end portions of the fins located between the dummy gates and adjacent active gates.
Also conventionally, the multiple Rx regions are separated by isolation regions, such as STI regions, that are typically composed of an amorphous dielectric material, such as a flowable oxide (FOX), and have a width of about 70 to 80 nanometers (nm). There can be many thousands to millions of such isolation regions providing electrical isolation between the many Rx regions in a typical ultra-high density integrated circuit.
However, as integrated circuits are scaled down to such class sizes as 14 nm node or beyond, the width of a conventional isolation region becomes increasingly problematic as a region devoid of active devices. Therefore, in an effort to reduce the width of prior art isolation regions, single dummy gates disposed within such isolation regions that can terminate two opposing fin arrays (i.e., fin-ends to fin-ends) between adjacent Rx regions have been developed. These specially designed dummy gates on top of isolation structure are known as Single Diffusion Breaks (SDB) and reduce the distance between Rx regions, that is the distance between fin array edges or fin-ends, i.e., the width of an isolation region, to about 30 nm.
However the formation of prior art SDBs problematically require extra masking, deposition and etching steps. Additionally, the process of making such SDBs are sensitive to lithographic alignment tolerances, which limit their scalability.
Moreover, the structure of prior art SDBs limits the epitaxial growth of the S/D regions abutting the SDB, resulting in S/D regions having a smaller epitaxial volume and electrical contact area compared to that of S/D regions located between active gates. The smaller S/D region volume and contact area can lead to greater contact resistance and degrade device performance.
Accordingly, there is a need for an SDB structure, and method of making the same, which is not as sensitive to lithographic alignment issues. Further there is a need for an SDB structure and method, which does not limit adjacently located S/D region epitaxial volume and contact area compared to other S/D regions located between active gates. Additionally, there is a need for an SDB structure and method, which can be scaled for the 14 nm node and beyond.